A full adder is a digital circuit that adds a pair of binary input bits and a carry-in bit to produce an output bit (the sum bit) and also a carry-out bit. In contrast, a half adder would merely add the pair of binary input bits without considering any carry-in bit. A full adder is commonly found in numerous digital circuits such as in arithmetic logic units. It is thus conventional in the design of a digital core to include numerous full adders. The power consumption, operating speed, and density of full adders is thus an important factor in the design of digital cores.
But circuit design of digital cores involves the use of a synthesis tool that converts register transfer level logic into standard cells that can then be physically arranged on a semiconductor substrate to form the desired integrated circuit. The synthesis tool must satisfy timing constraints that overwhelm other considerations such as increasing speed and reducing power consumption. The synthesis tool thus defaults to area and timing optimizations that neglect power consumption and speed goals. The resulting full adders from the synthesis tool then consume substantial power in an already thermally constrained environment. In particular, conventional full adders may include an internal circuit node that is shared by the circuit paths producing the carry-out bit and the sum bit. Such a circuit node will thus have substantial parasitic capacitance. The charging and discharging of the loaded internal circuit node then consumes power and slows operating speed. Alternatively, conventional full adders have a pair of logic gates to produce the sum signal (and another pair for producing the carry out signal). The contention between the logic gates with regard to driving the sum signal (or the carry-out signal) is solved through a corresponding pair of transmission gates controlled by the carry-in signal and its complement. But the transmission gates then introduce a struggle between their input and output that also consumes power and slows operating speed.
There is thus a need in the art for improved full adders having increased operating speed and reduced power consumption.